Zheng,Hong-Sheng

About Me

I'm Hong-Sheng Zheng, currently a quantum compiler engineer at Xanadu, focusing on quantum compilation technology. Prior to moving to Canada, I lived in Taiwan and worked at MediaTek as a compiler engineer specializing in AI and computer vision compiler design and optimization. I received my M.Sc. from the Department of Computer Science at National Chiao Tung University (NCTU), where I was advised by Prof. Wuu Yang.

Research Interests

• TinyML: focus on peak memory reduciton, compiler optimization
• Polyhedral Compiler: program anylsis, tiling and loop optimization
• Algo/Schedule Decoupled Compiler: Halide/TVM based schedule language and compiler design

News

• [10/2026] Recognized as a Top Reviewer for NeurIPS 2026 🏆
• [9/2026] Our paper on Backline, a heterogeneous compilation and runtime framework for quantum workloads across CPUs, GPUs, and FPGAs, is released on arXiv.
• [11/2025] New Blog section is added to the website 🎉
• [8/2025] Served as a reviewer for NeurIPS 2025, evaluating 5 machine learning papers on inference and training topics
• [1/2025] Our paper about multi-hierachy StreamNet inference in TinyML is accepted to TECS 2025.
• [10/2023] Our paper about memory-efficient optimiztion in TinyML is accepted to HPCA 2024.
• [9/2023] Our paper about hybrid(1D/2D) streaming approach applied on patch-based inference in TinyML is accepted to NeurIPS 2023.

Patents

• U.S. Pat. Appl. Pub. No. 2026/0169704 A1, “Method for Converting Multiple Scheduling Settings of a DAG of programming model into Program Code with Aid of a GUI,” filed Dec. 2024, published June 2026 (pending; first inventor; assignee: MediaTek Inc.)

Publications

Awards

• [2026] NeurIPS 2026 Top Reviewer.
• [2020] E.SUN bank Anti-Money Laundering Competition - Our team won third place.
• [2020] Irwin Mango Defects Classification Competition - Gain honorable mention.